High speed serial data communications (e.g., over serial data TX/RX links) are widely used to convey data over various channels, such as cables, board traces and backplanes. Examples of serial data communications include, without limitation, physical layer interface specifications (e.g., PCIe, SATA, GbE, XAUI, Gigabit Ethernet, USB, etc.) and memory data interface standards (e.g., DDR3, DDR4, LPDDR3, LPDDR4, etc.). With serial data communications, the transmitter usually does not share the same reference clock frequency as the one used by the receiver. This may be due to tolerance between crystal oscillators local to the transmitter or receiver can lead to frequency discrepancies. This may also be due to spread-spectrum modulation, which can cause variation in the phase and frequency of the transmitted signal and must be locally tracked.
As such, serial data communications receivers often use clock and data recovery (CDR) circuitry to recover (with low bit-error rate) an underlying clock signal in a data stream from a transmitter, track the data stream's phase, and decode the data stream accordingly. CDR circuitry generally recovers the underlying clock signal by sampling incoming data bits of the data stream (e.g., at its centers and at their transitions). CDR circuitry can include a phase interpolator (PI) to advance or delay tracking clock signals of the receiver, so as to adjust the effective frequency and phase of those tracking clock signals and generate all the sampling phases needed for recovery of the underlying clock signal. For example, when a tracking clock signal of the receiver leads the incoming data stream, a PI can adjust the local tracking clock so as to slow it down a bit, and when a tracking clock signal of the receiver lags the incoming data stream, the PI can adjust the local tracking clock so as to speed it up a bit. Such adjustments to the tracking clock signal may need be continuously made in order for it to tracking the incoming data stream.
One type of architecture for phase interpolators is current mode logic (CIVIL). With a phase interpolator of the CML type, in-phase (I) and quadrature (Q) clock signals and their complements are used as the reference clock signals. These clock signals are applied to switch on and off differential pairs of transistors coupled to weighted current sources. Some implementations use four differential pairs to generate an output phase value interpolated between any adjacent two of four reference phases corresponding to the differential pairs, such as 0°, 90°, 180°, and 270°.
Unfortunately, phase interpolators (PIs) suffer from their own impairments that can lead to timing errors, which in turn can prevent a receiver from re-sampling an incoming data stream at optimal time points. Integral non-linearity, differential non-linearity, and phase to quadrature skew (e.g., mismatch of an output phase to expected quadrature) can be just some of those impairments.